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    • 专利摘要:
    The invention relates to a method for producing a component comprising a structure of material (x) III-V on the surface of a substrate, said structure comprising at least one upper level of contact (Nsup) defined on the surface of a first III-V material (1) and a lower contact level (Ninf) defined on the surface of a second III-V material (2), comprising: - successive encapsulation operations with at least one dielectric (8 ) of said structure; - The realization of primary openings (Osp, Oip) in a dielectric for the two contacts; - Making secondary openings (Oss, Ois) in a dielectric for the two contacts; - At least partially filling with at least one metal material of said openings so as to achieve a higher contact bottom metallization and at least one upper contact pad in contact with said metallization for each of said contacts. The invention also relates to a component produced by said method. The component may be a laser diode.
    公开号:FR3061354A1
    申请号:FR1663133
    申请日:2016-12-22
    公开日:2018-06-29
    发明作者:Elodie GHEGIN；Christophe Jany；Fabrice Nemouchi；Philippe Rodriguez；Bertrand Szelag
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    @ Holder (s): COMMISSION FOR ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment.
    ® Agent (s): MARKS & CLERK FRANCE General partnership.
    ® PROCESS FOR PRODUCING A COMPONENT COMPRISING III-V MATERIALS AND COMPATIBLE CONTACTS OF THE SILICON INDUSTRY.
    FR 3,061,354 - A1 (57) The invention relates to a method for producing a component comprising a structure made of material (x) III-V on the surface of a substrate, said structure comprising at least one upper level of contact (N SLJp ) defined on the surface of a first material III-V (1) and a lower level of contact (N inf ) defined on the surface of a second material III-V (2), comprising:
    - successive operations of encapsulation by at least one dielectric (8) of said structure;
    - making primary openings (O S p; O ip ) in a dielectric for the two contacts;
    - the realization of secondary openings (O ss ; O is ) in a dielectric for the two contacts;
    - At least partial filling with at least one metallic material of said openings so as to produce a metallization of upper contact bottom and at least one upper contact pad in contact with said metallization for each of said contacts.
    The invention also relates to a component produced by said method. The component can be a laser diode.

    Method for producing a component comprising lll-V materials and compatible contacts of the silicon die
    The field of the invention is that of the co-integration of III-V materials on standard substrate such as silicon and which can be carried out on a silicon platform which can accommodate plates with a minimum diameter of 100 mm. The intended co-integration is part of an integration with a planarized back-end compatible with the Silicon 100 mm or more sector.
    The contacts currently integrated on lll-V materials use processes such as "lift-off" (the metal is deposited on the resin and the areas of interest then the resin is dissolved which removes the metal present above the resin by leaving the metal on the areas of interest) as well as a multitude of very expensive or prohibited metals in clean rooms Silicon as described in the article: A. Baca, F. Ren, J. Zolper, R. Briggs, and S. Pearton, “A survey of ohmic contacts to lll-V compound semiconductors,” Thin Solid Films, vol. 308-309, pp. 599-606, 1997, or in the article by G. Stareev, H. Kunzel, and G. Dortmann, “A controllable mechanism of forming extremely low-resistance nonalloyed ohmic contacts to group lll-V compound semiconductors,” Journal of Applied Physics, vol. 74, no. 12, p. 7344, 1993.
    Such non-planar integration does not open the way to the achievement of several higher levels or to the co-integration of other objects. The miniaturization and densification of the components are thus limited.
    Finally, the multiplication of the number of layers present in the current contacts (between 3 and 5), makes integration complex and not optimal. A typical example of non-planar contact integration is provided in the references: B. Ben Bakir, C. Sciancalepore, A. Descos, H. Duprez, D. Bordel, L. Sanchez, C. Jany, K. Hassan, P Brianceau, V. Carron, and S. Menezo, “Heterogeneously integrated lll-V on silicon lasers,” Meeting Abstracts, vol. MA2014-02, no. 34, p. 1724, 2014 and H. Duprez, A. Descos, T. Ferrotti, J. Harduin, C. Jany, T. Card, A. Myko, L. Sanchez, C. Sciancalepore, S. Menezo, and B. Ben Bakir, “Heterogeneously integrated lll-V on silicon distributed feedback lasers at
    1310 nm, ”in Optical Fiber Communications Conférence and Exhibition (OFC), 2015, pp. 1-3, March 2015.
    Figure 1 shows this type of configuration for laser application with non-planar contact pickups and compounds of noble metals for direct pickup on III-V materials. On an n-doped InP substrate, an active region structure based on MQW quantum multi-wells is produced, on which a p-doped InP layer and a p-doped InGaAs layer are stacked. Contacts are made via n-Pad contact pads to connect the n-doped substrate making it possible to define a lower contact and contacts made via p-Pad contact pads to connect the p doped layer of InGaAs, making it possible to define a superior contact.
    In this context, the present invention provides a method for making contacts on lll-V materials compatible in particular with the silicon sector, thereby allowing co-integration of lll-V / Silicon materials on a platform treating plates 100 mm in diameter at minimum.
    This invention thus opens the way to a finished product integrated in a silicon-compatible clean room processing plates of 100 mm or more, compact and having at least two levels of planar contacts made simultaneously or sequentially.
    More specifically, the subject of the present invention is a process for producing a component comprising a structure made of material (x) III-V on the surface of a substrate, said structure comprising at least one upper level of contact defined on the surface of a first material III-V and a lower level of contact defined on the surface of a second material III-V, comprising:
    - successive operations of encapsulation by at least one dielectric of said structure;
    - The production of at least one primary upper opening and at least one primary lower opening in a dielectric so as to define contact bottom zones on said first material III-V and on said second material IIIV;
    - The production of at least one secondary upper opening and at least one secondary lower opening in a dielectric so as to define zones of contact pads on said contact bottom zones;
    the at least partial filling with at least one metallic material of said at least primary upper opening, of said at least primary lower opening, of said at least secondary upper opening and of said at least secondary lower opening so as to produce:
    o at least one upper contact of said first material III-V in contact with the upper contact level and comprising at least one metallization of the upper contact bottom and at least one upper contact pad in contact with said metallization;
    o at least one lower contact of said second material III-V in contact with said lower contact level and comprising at least one bottom contact metallization and at least one lower contact pad in contact with said metallization;
    - At least said upper contact and at least said lower contact are integrated in dielectric and have a surface defined in the same plane.
    The planar character is thus defined as being the set of contacts emerging on the same plane.
    To achieve this result, the lower contacts (for the filling part) can be produced in one or more stages.
    We define by metallic material:
    - pure metals, metal alloys, metal alloys + non-metallic element;
    - intermetallic compounds (different from an alloy in its crystallographic construction).
    Planar-type integration opens the way to 3D integration, through hybrid or direct bonding (eg photonics / electronics) or the transfer of chips through bumps.
    In the context of an III-V / Si co-integration, the creation of a planarized back-end (corresponding to all of the stages constituting the interconnections by metal links) also makes it possible to envisage contact resumption on the lower level devices (back side front side or intermetallic for example).
    According to variants of the invention, the structure has a lower base made of second material III-V and a mesa made of first material III-V located above said base.
    According to variants of the invention, the method comprises successively producing at least one primary upper opening and at least one primary lower opening.
    It may be advantageous to independently optimize the contact metallizations on each of the materials present in the lll-V component in order to minimize the associated contact resistances.
    According to variants of the invention, the method comprises the simultaneous production of at least one secondary upper opening and at least one secondary lower opening.
    According to variants of the invention, the method comprises:
    - Encapsulation with a dielectric of an assembly comprising the first material III-V covered with a metallization and the second material III-V covered with a metallization;
    - the production of at least one secondary lower opening opposite the second lll-V material;
    - The production of at least one secondary upper opening above said first material III-V and the production of at least one additional secondary lower opening above at least said secondary lower opening;
    - filling at least said secondary upper opening, at least one additional secondary lower opening and at least said secondary lower opening.
    According to variants of the invention, the structure comprising at least one lll-V said upper material, a lll-V said intermediate material, a lll-V said lower material, the method comprises:
    - the production of at least one primary upper opening, at least one primary intermediate opening, at least one primary lower opening;
    - the production of at least one secondary upper opening, at least one secondary intermediate opening and at least one secondary lower opening;
    - filling of said openings.
    According to variants of the invention:
    - At least said secondary lower opening comprises three portions of different dimensions;
    - At least said secondary intermediate opening comprises two portions of different dimensions;
    - At least said secondary upper opening has a portion.
    According to variants of the invention, the method comprises the following steps:
    - the encapsulation of said structure by a first dielectric;
    - The production of at least one primary lower opening leading to said second material III-V;
    - The metallization deposit on the surface of said first dielectric and on the surface of said second semiconductor material defining a lower contact metallization and a first assembly;
    - the encapsulation of said first assembly by a second dielectric;
    - the planarization of said first encapsulated assembly;
    - the production of at least one secondary lower opening leading to said metallization of the lower contact bottom;
    - filling with at least one metallic material of said at least secondary lower opening defining at least one contact pad of said lower contact and a second assembly;
    - the encapsulation of said second set by a third dielectric;
    - The realization of at least one primary upper opening above said first material III-V;
    - The metallization deposit on the surface of said third dielectric material and of said upper opening defining a metallization of upper contact bottom and a third assembly;
    - the encapsulation of said third assembly by a fourth dielectric;
    - the planarization of said third set;
    - The production of at least one secondary upper opening above said metallization of the upper contact bottom and at least one upper opening above at least said contact pad of said lower contact;
    - filling with at least one metallic material of said at least secondary upper opening above said metallization of upper contact bottom and of said at least upper opening above at least said contact pad of said lower contact, defining at least one pad upper contact upper and at least one extension of lower contact pad, said upper contact and at least said lower contact having a surface defined in the same plane.
    According to variants, the method comprises the following steps:
    - the encapsulation of said structure by a first dielectric;
    - The production of at least one primary upper opening opening onto said first material III-V;
    - The metallization deposit on the surface of said first dielectric and on the surface of said first semiconductor material defining an upper contact metallization and a first assembly;
    - the encapsulation of said first assembly by a second dielectric;
    - the planarization of said first encapsulated assembly;
    - the production of at least one secondary upper opening leading to said metallization of the upper contact bottom;
    - filling with at least one metallic material of said at least secondary upper opening defining at least one contact pad of said upper contact and a second assembly;
    - The realization of at least one primary lower opening above said second material III-V;
    the metallization deposit on the surface of said first dielectric material and of said primary lower opening defining a lower contact metallization and a third assembly;
    - the encapsulation of said third assembly by a fourth dielectric;
    - the planarization of said third;
    - the production of at least one secondary lower opening above said bottom contact bottom layer;
    - Filling with at least one metallic material of said at least secondary lower opening, defining at least one lower contact pad, said upper contact and at least said lower contact having a surface defined in the same plane.
    According to variants, the method comprises:
    - the simultaneous production of at least one primary upper opening and at least one primary lower opening;
    - the simultaneous production of at least one secondary upper opening and at least one secondary lower opening.
    According to variants of the invention, the method comprises the production of an additional level of contact on the surface of said planar contacts, comprising:
    - an additional deposit of dielectric;
    - the production of at least one lower additional opening and at least one upper additional opening;
    - Filling said additional openings with at least one metallic material to define at least one lower additional contact and at least one upper additional contact.
    According to variants of the invention, the method comprises the production of primary lower openings having a width of between 20 μm and 50 μm and the production of secondary lower openings having a width of between 0.5 μm and 5 μm, preferably between 1 pm and 3 pm.
    According to variants of the invention, the first material III-V and the second material III-V are chosen from:
    The first material III-V can consist of material III-V such as InP, InvxGaxAs (with 0 <x <1), GaAs, InAs, of GaSb, In-i-xGaxSb, ln x Gai-xAsi-yPy, Gai - x ln x P, ln x Gai-xAsi-yNy, B x ln y Gai-x-yAs.
    The second material III-V can also consist of material III-V such as InP, InvxGaxAs (with 0 <x <1), GaAs, InAs, of GaSb, Ιη-ι-xGaxSb, ln x Gai-xAsi-yPy, Gai- x ln x P, ln x Gai-xAsi-yNy, B x ln y Gai-x-yAs ...
    According to variants of the invention, the substrate is made of silicon.
    According to variants of the invention, the dielectric or dielectrics are chosen from: SiN, SiO2, AI2O3, a planarizing polymer which can be based on Benzocyclobutene (BCB) or SOG.
    According to variants of the invention, a metal such as Ni 2 P, Ni 3 P, NiGe, TiP, TiGe is deposited in said primary openings.
    According to variants of the invention, a metal such as Ni, Ti and an alloy such as NiPt, NiTi, NiCo is deposited in said primary openings.
    According to variants of the invention, the filling operations include:
    - the deposition of a diffusion barrier which may be composed of one or more layers of material chosen from: TiN, Ti / TiN, TaN, Ta / TaN, W (fluorine-free);
    - the deposition of a filler metal chosen from: W, Cu, Al, AlCu, AlSi.
    Regarding the diffusion barrier, W is fluorine-free because the barrier is deposited by CVD (chemical route), the precursor of which does not contain F, unlike the filling W. The F being harmful for the devices this is why a barrier is used. This barrier can also be used to facilitate nucleation of the filling metal (W, Cu, Al ...).
    The element W is particularly advantageous in the context of the present invention because it is not very resistive and easy to implement, it can thus be advantageously used to fill the secondary openings.
    According to variants of the invention, the metallization deposit is followed by a heat treatment intended to form one or more intermetallic compound (s).
    According to variants of the invention, the component being a laser, the method of the invention comprises an operation for producing a guide in semiconductor material which may be Si, in a dielectric substrate which may be in SiO 2 .
    According to variants of the invention, the component being a laser, the method of the invention comprises producing a circular upper contact to allow the vertical emission of the laser radiation.
    The invention also relates to the component obtained according to the process of the invention.
    The component can be a wafer emission or vertical emission laser. It can also advantageously be a component comprising a series of different lll-V materials having different absorption wavelengths to widen the absorption band of the component.
    The present invention can be applied to a multitude of starting configurations, such as:
    - III-V reports on any type of substrate, for example on Si plate chips;
    - plates to plates;
    - epitaxies of lll-V on Si, lll-V substrate, or any permanent or temporary substrate allowing crystal growth of lll / V. It should be noted that it is advisable to have at least one crystalline germ of crystallographic structure identical to that of the material III / V which one wants to make grow and of the parameters of mesh close to the growing layer. Beyond 5% difference between the mesh parameters, the crystal is defective (dislocation, antiphase joint or even polycrystalline). This is impossible on an amorphous glass type substrate.
    The starting substrates can be 100 mm or more in diameter.
    The invention will be better understood and other advantages will appear on reading the description which follows given without limitation and thanks to the appended figures among which:
    - Figure 1 illustrates an example of a component based on lll-V materials of the prior art;
    - Figure 2 illustrates an example of a structure of III-V materials on substrate used in examples of the process of the invention;
    - Figure 3 illustrates an example of a component produced in the context of the present invention;
    - Figures 4a to 4o illustrate the different stages of a first example of the process of the invention comprising the production of the lower contacts then that of the upper contacts;
    - Figures 5a to 5n illustrate the different stages of a second example of the method of the invention comprising the production of the upper contacts then that of the lower contacts;
    - Figures 6a to 6h illustrate the different stages of a third example of the method of the invention comprising the simultaneous production of the upper and lower contacts;
    - Figures 7a to 7d illustrate the different stages of a fourth example of the method of the invention comprising the simultaneous production of upper and lower secondary openings at two levels;
    - Figure 8 illustrates a step of integrating an additional level of contact that can be used in alternative process of the invention;
    FIG. 9 illustrates a first example of a laser component produced according to the method of the invention:
    - Figure 10 illustrates a second example of a laser component produced according to the method of the invention;
    - Figure 11 illustrates an example of a component obtained according to the method of the invention in the context of photonic integration;
    - Figure 12 illustrates an example of an absorbent component in different wavelength ranges through the use of at least three different levels of III-V materials, and produced according to the method of the invention.
    In the detailed description below described various embodiments of the invention are described.
    Contact integration is presented on two levels but is applicable to a multitude of levels presenting between them a topography of different contact levels at the level of materials III-V.
    The invention is described below in the context of a substrate 9 on which a structure is made comprising a basic III-V material 2 and a higher III-V material 1 as illustrated in FIG. 2, in which it is possible to produce a mesa having a surface smaller than that of the basic material III-V.
    In the whole of the description reference is made below:
    - a first material III-V: 1;
    - a second material III-V: 2;
    - a substrate: 9;
    - one or more dielectric material (s): 8;
    - a metallization: 3;
    - a diffusion barrier: 4;
    - a metallic filling material: 5;
    An upper contact C sup is defined from at least one primary upper opening O sp and from at least one secondary upper opening O ss
    An intermediate contact Cint is defined from at least one primary intermediate opening O tp and from at least one secondary intermediate opening O ts .
    A lower contact Cint is defined from at least one primary lower opening Oj P and at least one secondary lower opening Oi S.
    Generally, a metallization of the primary opening bottom and a contact pad in a secondary opening are defined. The contact thus consists of at least the metallization of the opening bottom and of the contact pad in contact with said metallization.
    FIG. 3 shows an example of a component highlighting, on a substrate 9, the materials III-V 1 and 2, metallizations 3 serving as contact bottom metallizations, on which are made contact pads comprising diffusion barriers 4, the secondary openings are filled with filling metal 5. The assembly is encapsulated in a dielectric 8. FIG. 3 highlights the contact levels: a lower level N in f, an upper level N sup . According to this example, an additional level N sup / sup i can be provided on which can be made contact pads filled with diffusion barrier 7 and filling metal 6.
    The first material III-V can consist of material III-V such as InP, In ^ xGaxAs (with 0 <x <1), GaAs, InAs, of GaSb, In-i-xGaxSb, ln x Gai- x Asi- yPy, Ga- |. x ln x P, ln x Gai- x Asi- y N y , B x ln y Gai- x - y As.
    The second material III-V can also consist of material III-V such as InP, In ^ xGaxAs (with 0 <x <1), GaAs, InAs, of GaSb, ln- |. x Ga x Sb, ln x Gai- x Asi- y P y , Ga- |. x ln x P, ln x Gai- x Asi- y N y , B x ln y Gai- x - y A. It can be identical to the first material or different from the latter.
    According to the present invention, the upper levels of the upper (s) and lower (s) contacts are located in the same plane.
    First example of a process according to the invention comprising the production of lower contacts followed by that of upper contact:
    The figures relating to this example show sectional views of contacts which may be circular or linear.
    First stage :
    The structure is carried out beforehand and comprising a mesa made of a first material III-V 1 on the surface of a base made of a material III-V 2 on a substrate 9.
    The dielectric (s) 8 used can be: SiN, SiO 2 , AI 2 O 3 , polymer of planarizing type, for example based on benzocyclobutane (BCB), or of type: SOG “Spin-On-Glass”: dielectric deposition amorphous by centrifugation.
    The deposit can be monolayer or multilayer.
    Dielectrics are deposited by PVD (physical vapor deposition), CVD (chemical vapor deposition) and / or ALD (atomic thin film deposition. Typically the deposition temperature can be <550 ° C, preferably ^ 450 ° C .
    The stress of the layers produced can advantageously be <200 MPa, preferably <100 MPa.
    Figure 4a illustrates this encapsulation step.
    Second step :
    The dielectric is planarized by a CMP operation for “chemical mechanical planarization” or “chemical mechanical polishing” or partial removal by etch back in the case of a planarizing polymer
    There are certain polymers which have the property of being self-leveling. That is, they will fill the lower parts first before the upper parts. But to be sure to fill the cavities entirely the deposit is thicker than the depth of the cavity. It is then necessary to reduce the thickness of the excess deposit. This can be done by dry etching the entire plate called "etch back".
    It is also possible to use a lithography / etching operation located on the topography before CMP.
    Figure 4b illustrates this planarization step.
    Third step :
    We proceed to the realization of primary lower openings Ο, ρ dedicated to the lower contact.
    Typically the dimensions D1, D2, D3 and D4 can be as follows:
    The dimension D1 (width of dielectric on either side of the mesa of material III-V 1) is at least 200 nm and preferably between 2 and 3 μm.
    The dimension D2 (width of the primary lower openings) can be between 20 and 50 μm.
    The dimension D3 (dielectric thickness) is between 0.5 μm and 5 μm, preferably between 5 and 3 μm.
    The dimension D4 (central width between the two primary lower openings) can be between 0.5 pm and 10 pm, preferably between 1 and 5 pm
    For this, localized etching of the dielectric is carried out (in the case of several layers) to lead to the material III-V 2. It is possible to carry out the etching in one go to the material III-V 2 by a dry etching operation. . In this case, the presence of an etching stop layer is optional.
    It is also possible to carry out sequential etching operations: a first dry etching used to etch part of the dielectric stack with stopping on a stopping layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC preferably SiN ) then use a dry or wet etching to etch the stop layer and any underlying layers and lead to the material III-V 2.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or preferably using a hard mask composed for example of SiN.
    This step of making openings is illustrated in FIG. 4c.
    Fourth step:
    We proceed to the deposition of a metallization compatible with a silicon die to define the lower contact making it possible to avoid the use of noble metals, metals not used by the silicon die.
    Metallization compatible with a silicon die can be carried out according to two options:
    - option 1:
    (a) depositing a metal 3 compatible with a silicon die such as Ni 2 P, Ni 3 P, NiGe, TiP, TiGe, etc.;
    The phases can be stabilized by an optional heat treatment carried out after the metal deposition;
    (b) depositing a metal 3 compatible with a silicon die such as Ni, Ti and an alloy such as NiPt, NiTi, NiCo, etc .;
    - option 2: we deposit a metal compatible with a silicon die (Ni, Ti and their alloys); then a heat treatment is carried out with the aim of carrying out a reaction in the solid state between the metal and the III-V material leading to the formation of one or more intermetallic compound (s).
    The deposition temperatures are preferably <450 ° C. The annealing temperature is preferably <450 ° C. According to option 1, the metal or the intermetallic compound is deposited and the work of output of the latter is used. In this case the annealing serves to cure the interface defects and to crystallize the metal or the compound.
    According to option 2, the metal is deposited, it is reacted to form the intermetallic compound having the intended output work. In this case the annealing is used for the reaction in the solid state.
    Selective removal of unreacted metal may be performed after heat treatment.
    We then obtain an assembly E1 illustrated in FIG. 4d.
    Fifth step:
    A step of encapsulation of the assembly E1 is carried out with dielectric 8. The dielectric (s) used can be: SiN, SiO 2 , AI 2 O 3 , polymer of planarizing type (for example BCB, SOG ). The deposit can be monolayer or multilayer. They are filed by PVD, CVD and / or ALD;
    The deposition temperature is <450 ° C, preferably <300 ° C.
    This step is illustrated in Figure 4e.
    The phase stabilization or heat treatment operations to form one or more intermetallic compound (s) can be carried out at the end of this stage, if they have not been carried out at the end of the fourth stage .
    Sixth step:
    The dielectric is planarized by a CMP operation or an "etch back" type operation in the case of a planarizing polymer.
    CMP or "etch back" planarization can be carried out:
    - if the selective removal has not been carried out in the fourth step, until the removal of the metal;
    - if selective removal has not been carried out in the fourth step, and if the CMP or "etch back" operation of the metal is impossible, with stopping on the metal. The selective metal removal step can then be carried out to obtain a structure as illustrated in FIG. 4f;
    - if the selective removal was carried out in the fourth step, until obtaining a structure as illustrated in Figure 4f.
    Typically, the height D5 shown (thickness of dielectric above the material III-V 1) can be between 200 nm and 1 μm.
    The phase stabilization or heat treatment operations to form one or more intermetallic compound (s) can be carried out at the end of this stage, if they have not been carried out at the end of the fourth stage or at the end of the fifth stage.
    Seventh step:
    We carry out an operation of upper secondary lower openings Oj S i intended for connection pads. For this, an etching of the dielectric stack is carried out to lead to metallization 3 at the lower level.
    Etching is carried out in one go until metallization: dry etching. In this case, the presence of an etching stop layer is optional.
    We can proceed with sequential etchings: a first dry etch is used to etch part of the dielectric stack with stop on a stop layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC, preferably SiN), then a dry or wet etching is used to etch the barrier layer and any underlying layers and lead to metallization 3.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or using a hard mask composed for example of SiN. Typically the dimension D6 (width of the secondary lower openings) shown as a dielectric can be between 0.5 μm and 5 μm and preferably between 1 μm and 3 μm. This step is illustrated in Figure 4g.
    Eighth step:
    We fill the secondary lower openings and CMP operation to make connection pads. The filling of the secondary lower openings is done in two stages:
    - a diffusion barrier / a bonding or nucleation layer 4 is deposited. It can be composed of TiN, Ti / TiN, TaN, Ta / TaN or W deposited by CVD, PVD or ALD ;
    - a filling metal 5 (W, Cu, AlCu, AISi) deposited by CVD, ECD or PVD is deposited.
    A CMP operation is finally performed to decontact the pads. Since the metal is present at the top of the cavities between two studs, a short circuit is therefore inevitable. The CMP operation removes only the metal from the studs and therefore decontacts.
    We constitute a new set E2. All of these steps are illustrated in Figure 4h.
    Ninth stage:
    An encapsulation operation is carried out with a dielectric 8. The dielectric (s) used can be: SiN, SiO 2 , AI 2 O 3 , a polymer of planarizing type (for example BCB, SOG). The deposit can be monolayer or multilayer. The dielectrics are deposited by PVD, CVD and / or ALD. The deposition temperature <450 ° C., preferably ^ 300 ° C. Typically the height D7 shown of dielectric can be between 200 nm and 1 μm and preferably between 200 nm and 500 nm. This step is illustrated in Figure 4i.
    Tenth step:
    We proceed to the realization of primary upper opening O sp to achieve a higher contact.
    The dielectric stack is etched to lead to the lll-V 1 material. The etching can be carried out at once to the lll-V 1 material by dry etching. In this case, the presence of an etching stop layer is optional.
    We can proceed to sequential etchings: a first dry etching is used to etch part of the dielectric stack with stop on a stop layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC preferably SiN) then dry etching or wet is used to etch the barrier layer and any underlying layers and lead to the lll-V 1 material.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or preferably using a hard mask composed for example of SiN.
    This step is illustrated in Figure 4j.
    Eleventh step:
    One proceeds to the deposition of metallization 3 compatible with a silicon die intended for the upper contact. Metallization compatible with a silicon die can be achieved in two ways:
    - option 1:
    (a) depositing a metal 3 compatible with a silicon die such as Ni 2 P, Ni 3 P, NiGe, TiP, TiGe, etc.;
    The phases can be stabilized by an optional heat treatment carried out after the metal deposition;
    (b) depositing a metal 3 compatible with a silicon die such as Ni, Ti and an alloy such as NiPt, NiTi, NiCo, etc .;
    - option 2: we deposit a metal compatible with a silicon die (Ni, Ti and their alloys); then a heat treatment is carried out with the aim of carrying out a reaction in the solid state between the metal and the III-V material leading to the formation of one or more intermetallic compound (s).
    The annealing temperature is preferably <450 ° C
    Selective removal of unreacted metal may be performed after heat treatment. We obtain a third set E3.
    This step is illustrated in Figure 4k.
    Twelfth step:
    The third set E3 is encapsulated. The dielectric (s) used can be: SiN, SiO 2 , AI 2 O 3 , planarizing type polymer (for example BCB), SOG. The deposit can be monolayer or multilayer. They are filed by PVD, CVD and / or ALD. The deposition temperature <450 ° C, preferably ^ 300 ° C.
    This step is illustrated in Figure 4L
    The phase stabilization or heat treatment operations to form one or more intermetallic compound (s) can be carried out at the end of this stage, if they have not been carried out at the end of the eleventh stage .
    Thirteenth step:
    We proceed to a planarization operation.
    Planarization or etch back can be carried out:
    - if the selective removal has not been carried out in the eleventh step, until the removal of the metal;
    - if the selective removal was not carried out at the eleventh step, and if the operation of CMP or "etch back" of the metal is impossible, with stop on the metal. The selective metal removal step can then be carried out to obtain a structure as shown in FIG. 4m;
    - if the selective removal was carried out in the eleventh step, until obtaining the structure illustrated in Figure 4m.
    The phase stabilization or heat treatment operations to form one or more intermetallic compound (s) can be carried out at the end of this stage, if they have not been carried out at the end of the eleventh stage or at the end of the twelfth stage.
    Fourteenth step:
    The secondary upper opening O ss is produced and the additional upper openings Oi S 2 are produced above at least the contact pads of a lower contact.
    The dielectric stack is etched to lead to the metallization of the upper contact level and to the contact pads of the lower contact.
    Etching is carried out in one go up to metallization 3 and up to the studs on the lower level, by dry etching. In this case, the presence of an etching stop layer is optional.
    Sequential etching operations can be carried out: a first dry etching is used to etch part of the dielectric stack with stopping on a stopping layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC, preferably SiN) on metallization of the upper contact bottom and on the pads of the lower contact;
    Dry or wet etching can be used to etch the barrier layer and any underlying layers and lead to metallization 3.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or using a hard mask composed for example of SiN.
    This step is illustrated in Figure 4n.
    Fifteenth step:
    We fill the openings defined in the previous step.
    The filling of the openings is carried out in two stages:
    - we deposit a deposit of a diffusion barrier / a bonding or nucleation layer. It can be composed of TiN, Ti / TiN, TaN, Ta / TaN or W deposited by CVD, PVD or ALD;
    - a filler metal (W, Cu, AlCu, AlSi ..) is deposited by CVD, ECD or PVD.
    A CMP operation is finally performed to decontact the pads.
    This step is illustrated in FIG. 4o and leads to the production of the upper C sup and lower Ci n t contacts.
    An alternative to the first example of a method can comprise a sequential production of the primary openings coupled with a simultaneous production of the secondary openings.
    Second example of a process according to the invention comprising the production of upper contacts followed by that of lower contacts:
    First stage :
    The structure is carried out beforehand and comprising a mesa made of a first material III-V 1 on the surface of a base made of a material III-V 2 on a substrate 9.
    The dielectric (s) 8 used can be: SiN, SiO 2 , AI 2 O 3 , polymer of planarizing type (for example BCB, SOG).
    The deposit can be monolayer or multilayer.
    The dielectrics are deposited by PVD, CVD and / or ALD. Typically the deposition temperature can be <450 ° C, preferably <300 ° C.
    The stress of the layers produced can be <200 MPa, preferably <100 MPa. Figure 5a illustrates this encapsulation step.
    Second step :
    The dielectric is planarized by an operation of the CMP type or of the "etch back" type in the case of a planarizing polymer. It is also possible to use a lithography / engraving operation located on the topography before CMP. Figure 5b illustrates this planarization step.
    Third step :
    We proceed to the realization of primary upper opening O sp dedicated to the upper contact.
    For this, localized etching of the dielectric is carried out (in the case of several layers) to lead to the material III-V 1. The etching can be carried out in one go to the material III-V 1 by a dry etching operation. . In this case, the presence of an etching stop layer is optional.
    It is also possible to carry out sequential etching operations: a first dry etching used to etch part of the dielectric stack with stopping on a stopping layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC preferably SiN) then use dry or wet etching to etch the barrier layer and any underlying layers and lead to the material III-V 1.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or preferably using a hard mask composed for example of SiN.
    This step of making openings is illustrated in FIG. 5c.
    Fourth step:
    We proceed to the deposition of a metallization 3 compatible with a silicon die on the material III-V 1.
    Metallization can be carried out according to two options: option 1:
    (a) depositing a metal 3 compatible with a silicon die such as Ni 2 P, Ni 3 P, NiGe, TiP, TiGe, etc.;
    The phases can be stabilized by an optional heat treatment carried out after the metal deposition;
    (b) depositing a metal 3 compatible with a silicon die such as Ni, Ti and an alloy such as NiPt, NiTi, NiCo, etc .;
    option 2: we deposit a metal compatible with a silicon die (Ni, Ti and their alloys); then a heat treatment is carried out with the aim of carrying out a reaction in the solid state between the metal and the III-V material leading to the formation of one or more intermetallic compound (s).
    The annealing temperature is preferably <450 ° C.
    Selective removal of unreacted metal may be performed after heat treatment.
    We then obtain a set ΕΓ illustrated in FIG. 5d.
    Fifth step:
    A step of encapsulation of the assembly ΕΓ is carried out with dielectric 8. The dielectric (s) used can be: SiN, SiO 2 , AI 2 O 3 , polymer of planarizing type (for example BCB, SOG ). The deposit can be monolayer or multilayer. They are filed by PVD, CVD and / or ALD;
    Deposition temperature <450 ° C, preferably ^ 300 ° C. This step is illustrated in Figure 5e.
    The phase stabilization or heat treatment operations to form one or more intermetallic compound (s) can be carried out at the end of this stage, if they have not been carried out at the end of the fourth stage .
    Sixth step:
    The dielectric is planarized by an operation of the CMP type or of the "etch back" type in the case of a planarizing polymer. These operations can be carried out:
    - if the selective removal has not been carried out in the fourth step, until the removal of the metal;
    - if the selective removal was not carried out in the fourth step, and if the operation of the CMP type or of the "etch back" type of the metal is impossible, with stopping on the metal. The selective metal removal step can then be carried out to obtain a structure as illustrated in FIG. 5f;
    - if the selective removal was carried out in the fourth step, until obtaining a structure as illustrated in Figure 5f.
    The phase stabilization or heat treatment operations to form one or more intermetallic compound (s) can be carried out at the end of this stage, if they have not been carried out at the end of the fourth stage or at the end of the fifth stage.
    Seventh step:
    We carry out an operation of secondary upper openings Oss intended for the connection pads. For this, an etching of the dielectric stack is carried out to lead to metallization 3 at the upper level.
    The etching is carried out at once until metallization can be by dry etching. In this case, the presence of an etching stop layer is optional.
    We can proceed with sequential etchings: a first dry etch is used to etch part of the dielectric stack with stop on a stop layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC, preferably SiN), then a dry or wet etching is used to etch the barrier layer and any underlying layers and lead to metallization 3.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or using a hard mask composed for example of SiN.
    This step is illustrated in Figure 5g.
    Eighth step:
    The O ss openings are filled and a CMP operation is carried out to make connection pads.
    The filling of the O ss openings is done in two stages:
    - we proceed with the deposition of a diffusion barrier / a bonding or nucleation layer. It can be composed of TiN, Ti / TiN, TaN, Ta / TaN or W deposited by CVD, PVD or ALD;
    - a filler metal (W, Cu, AlCu, AISi, ...) is deposited by CVD, ECD or PVD.
    A CMP is finally performed to decontact the studs. We are building a new E2 set. All of these steps are illustrated in Figure 5h.
    Ninth stage:
    We proceed to the realization of primary lower openings Ο, ρ to achieve lower contacts.
    The dielectric stack is etched to lead to the lll-V 2 material. The etching can be carried out at once to the lll-V 2 material by dry etching. In this case, the presence of an etching stop layer is optional.
    We can proceed to sequential etchings: a first dry etching is used to etch part of the dielectric stack with stop on a stop layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC preferably SiN) then dry etching or wet is used to etch the barrier layer and any underlying layers and lead to the lll-V 2 material.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or preferably using a hard mask composed for example of SiN.
    This step is illustrated in Figure 5i.
    Tenth step:
    We proceed to the deposition of metallization 3 compatible with a silicon die intended for the lower contacts. CMOS-compatible metallization can be achieved in two ways:
    One proceeds to the deposition of metallization 3 compatible with a silicon die intended for the upper contact. Metallization can be achieved in two ways:
    option 1:
    (a) depositing a metal 3 compatible with a silicon die such as Ni 2 P, Ni 3 P, NiGe, TiP, TiGe, etc.;
    The phases can be stabilized by an optional heat treatment carried out after the metal deposition;
    (b) depositing a metal 3 compatible with a silicon die such as Ni, Ti and an alloy such as NiPt, NiTi, NiCo, etc .;
    option 2: we deposit a metal compatible with a silicon die (Ni, Ti and their alloys); then a heat treatment is carried out with the aim of carrying out a reaction in the solid state between the metal and the III-V material leading to the formation of one or more intermetallic compound (s).
    The deposition temperatures are preferably <450 ° C.
    The annealing temperature is preferably <450 ° C
    Selective removal of unreacted metal may be performed after heat treatment. We get a third set E3 ’.
    This step is illustrated in Figure 5j.
    Eleventh step:
    A step of encapsulation of the assembly E3 ’is carried out with dielectric 8. The dielectric (s) used can be: SiN, S1O2, AI2O3, polymer of planarizing type (for example BCB), SOG. The deposit can be monolayer or multilayer. They are filed by PVD, CVD and / or ALD;
    Deposition temperature <450 ° C, preferably ^ 300 ° C.
    This step is illustrated in Figure 5k.
    The phase stabilization or heat treatment operations to form one or more intermetallic compound (s) can be carried out at the end of this stage, if they have not been carried out at the end of the tenth stage .
    Twelfth step:
    A dielectric planarization operation is carried out by a CMP type or “etch back” type operation in the case of a planarizing polymer.
    This step is illustrated in Figure 51.
    The phase stabilization or heat treatment operations to form one or more intermetallic compound (s) can be carried out at the end of this stage, if they have not been carried out at the end of the tenth stage or at the end of the twelfth stage.
    Thirteenth step:
    We do a secondary lower opening operation
    Ois intended for connection pads. For this, an etching of the dielectric stack is carried out to lead to metallization 3 at the lower level.
    Etching is carried out in one go until metallization by dry etching. In this case, the presence of an etching stop layer is optional.
    We can proceed with sequential etchings: a first dry etch is used to etch part of the dielectric stack with stop on a stop layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC, preferably SiN), then a dry or wet etching is used to etch the barrier layer and any underlying layers and lead to metallization 3.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or using a hard mask composed for example of SiN. Typically the height D6 shown of dielectric can be between 0.5 μm and 5 μm and preferably between 1 μm and 3 μm.
    This step is illustrated in Figure 5m.
    Fourteenth step:
    We fill the openings defined in the previous step.
    The filling of the openings is carried out in two stages:
    - we deposit a deposit of a diffusion barrier / a bonding or nucleation layer. It can be composed of TiN, Ti / TiN, TaN, Ta / TaN or W deposited by CVD, PVD or ALD;
    - a filler metal (W, Cu) deposited by CVD, ECD or PVD is deposited.
    A CMP operation is finally performed to decontact the pads.
    This step is illustrated in FIG. 5n and leads to the production of the upper C sup and lower Ci n t contacts.
    An alternative to the second example of a method can comprise a sequential production of the primary openings coupled with a simultaneous production of the secondary openings.
    Third example of a method according to the invention comprising the simultaneous production of upper contact and lower contact:
    First stage :
    The structure is carried out beforehand and comprising a mesa made of a first material III-V 1 on the surface of a base made of a material III-V 2 on a substrate 9.
    The dielectric (s) 8 used can be: SiN, SiO 2 , AI 2 O 3 , polymer of planarizing type (for example BCB, SOG).
    The deposit can be monolayer or multilayer.
    The dielectrics are deposited by PVD, CVD and / or ALD. Typically the deposition temperature can be <450 ° C, preferably <300 ° C.
    The stress of the layers produced can be <200 MPa, preferably <100 MPa. Figure 6a illustrates this encapsulation step.
    Second step :
    The dielectric is planarized by an operation of the CMP type or of the "etch back" type in the case of a planarizing polymer. It is also possible to use a lithography / engraving operation located on the topography before CMP. Figure 6b illustrates this planarization step.
    Third step :
    We proceed to the production of primary lower openings Ο, ρ dedicated to the lower contact and to a primary upper opening O sp dedicated to the upper contact.
    For this, localized etching of the dielectric (in the case of several layers) is carried out to lead to the material III-V 2 and to lead to the material III-V 1.
    Etching can be carried out at one time up to material IIIV 2 and up to material 1 by a dry etching operation. In this case, the presence of an etching stop layer is optional.
    It is also possible to carry out sequential etching operations: a first dry etching used to etch part of the dielectric stack with stopping on a stopping layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC preferably SiN) then use dry or wet etching to etch the barrier layer and any underlying layers and lead to the material III-V 2 and to the material III-V 1.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or preferably using a hard mask composed for example of SiN.
    This step of making openings is illustrated in FIG. 6c.
    Fourth step:
    We proceed to the deposition of a metallization 3 compatible with a silicon die on the material III-V 1 and on the material III-V 2.
    One proceeds to the deposition of metallization 3 compatible with a silicon die intended for the upper contact. Metallization can be achieved in two ways:
    option 1:
    (a) depositing a metal 3 compatible with a silicon die such as Ni 2 P, Ni 3 P, NiGe, TiP, TiGe, etc.;
    The phases can be stabilized by an optional heat treatment carried out after the metal deposition;
    (b) depositing a metal 3 compatible with a silicon die such as Ni, Ti and an alloy such as NiPt, NiTi, NiCo, etc .;
    - option 2: we deposit a metal compatible with a silicon die (Ni, Ti and their alloys); then a heat treatment is carried out with the aim of carrying out a reaction in the solid state between the metal and the III-V material leading to the formation of one or more intermetallic compound (s).
    The annealing temperature is preferably <450 ° C
    Selective removal of unreacted metal may be performed after heat treatment.
    We then obtain a set E1 ”illustrated in Figure 6d.
    Fifth step:
    A step of encapsulation of the assembly E1 ”is carried out with dielectric 8. The dielectric (s) used can be: SiN, SiO 2 , AI 2 O 3 , polymer of planarizing type (for example BCB, SOG). The deposit can be monolayer or multilayer. They are filed by PVD, CVD and / or ALD;
    The deposition temperature is <450 ° C, preferably <300 ° C.
    This step is illustrated in Figure 6e.
    The phase stabilization or heat treatment operations to form one or more intermetallic compound (s) can be carried out at the end of this stage, if they have not been carried out at the end of the fourth stage .
    Sixth step:
    The dielectric is planarized by an operation of the CMP type or of the "etch back" type in the case of a planarizing polymer. These operations can be carried out:
    - if the selective removal has not been carried out in the fourth step, until the removal of the metal;
    - if selective removal has not been carried out in the fourth step, and if the CMP or "etch back" operation of the metal is impossible, with stopping on the metal. The selective metal removal step can then be carried out to obtain a structure as illustrated in FIG. 6f;
    - if the selective removal was carried out in the fourth step, until obtaining a structure as illustrated in Figure 6f.
    The phase stabilization or heat treatment operations to form one or more intermetallic compound (s) can be carried out at the end of this stage, if they have not been carried out at the end of the fourth stage or at the end of the fifth stage.
    Seventh step:
    We do a secondary upper opening operation
    Oss and Oj S secondary lower openings intended for connection pads. For this, an etching of the dielectric stack is carried out to lead to metallization 3 at the upper level and at the lower level.
    Etching is carried out in one go until metallization by dry etching. In this case, the presence of an etching stop layer is optional.
    We can proceed with sequential etchings: a first dry etch is used to etch part of the dielectric stack with stop on a stop layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC, preferably SiN), then a dry or wet etching is used to etch the barrier layer and any underlying layers and lead to metallization 3.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or using a hard mask composed for example of SiN.
    This step is illustrated in Figure 6g.
    Eighth step:
    We fill the openings defined in the previous step.
    The filling of the openings is carried out in two stages:
    - we deposit a deposit of a diffusion barrier / a bonding or nucleation layer. It can be composed of TiN, Ti / TiN, TaN, Ta / TaN or W deposited by CVD, PVD or ALD;
    - a filler metal (W, Cu) deposited by CVD, ECD or PVD is deposited.
    A CMP operation is finally performed to decontact the pads.
    This step is illustrated in FIG. 6h and leads to the production of the upper contacts C sup and lower contacts Ci n t.
    An alternative to the three examples of methods described above consists in making contact pads having several sections for the lower contact.
    Fourth example process
    First stage :
    An assembly is carried out according to sub-steps identical to those previously described, comprising:
    - a substrate 9;
    - a material III-V 1;
    - a III-V 2 material;
    - metallizations 3;
    The assembly is encapsulated in a dielectric 8 and is illustrated in FIG. 7a.
    Second step :
    We proceed to the production of secondary lower openings O is i by partial etching of the preconstituted assembly, or by partial etching of the dielectric 8. We can proceed by dry etching. In this case, the presence of an etching stop layer is optional.
    This (these) etching (s) can (can) be carried out directly via a resin used for photolithography or using a hard mask composed for example of SiN.
    This step is illustrated in Figure 7b.
    Third step :
    A second etching operation is carried out in a second step in order to extend the secondary lower openings, by carrying out the openings Oi S 2 in the extension of the previously made openings Oj S i, and in producing secondary upper openings O ss de so as to lead to metallizations 3.
    The etching operation can be carried out at once until metallization and this by dry etching. In this case, the presence of an etching stop layer is optional.
    Preferably, it is possible to carry out sequential etching operations: a first dry etching used to etch part of the dielectric stack with stopping on a stopping layer (SiN, AI 2 O 3 , SiO 2 , BCB, SOC, preferably SiN) then use of dry or wet etching to etch the barrier layer and any underlying layers and lead to the metallizations.
    This (these) etching (s) can (can) be carried out directly via the resin used for photolithography or using a hard mask composed for example of SiN.
    This step is illustrated in Figure 7c.
    Fourth step:
    We fill the openings defined in the previous step.
    The filling of the openings is carried out in two stages:
    - we deposit a deposit of a diffusion barrier / a bonding or nucleation layer. It can be composed of TiN, Ti / TiN, TaN, Ta / TaN or W deposited by CVD, PVD or ALD;
    - a filler metal (W, Cu, AlCu, AISi) is deposited by CVD, ECD or PVD.
    A CMP operation is finally performed to decontact the pads.
    This step is illustrated in FIG. 7d and leads to the production of the upper contacts C sup and lower contacts Ci n t.
    In general, it is possible to make an additional level of contact on the surface of the planar contacts previously developed and in particular described in the previous examples of process according to the invention.
    A complementary step can thus be carried out by carrying out an additional deposit of dielectric 8, then with the realization of additional upper and lower openings by etching and the filling of these openings to define the contacts C in f / su P i and C sup / supi as illustrated in figure 8.
    For this, we proceed, in the upper and lower additional openings, to deposit a barrier 7 which may be made of TiN,
    Ti / TiN, TaN, Ta / TaN, W and filling with a metal 6 which may be W, Cu or Al, AlCu, AlSi.
    It should be noted that the additional level of contact can also be achieved by etching a metal stack previously produced via a resin or a hard mask.
    Example of a laser component produced according to the method of the invention:
    The process of the present invention advantageously makes it possible to produce a laser based on III-V materials:
    A SiO 2 substrate 90 comprises a silicon guide 91 above which are produced:
    - a base of second material III-V 2, which can be made of n-doped InP and a mesa 1 comprising a quantum multi-well structure which can be made of InGaAsP with different dopings and a layer of p-doped InGaAs, the nature of the materials III-V fixed the emission wavelength;
    the dielectric 8 can be made of SiN, SiO 2 , of a polymer of the planarizing type, for example based on BCB;
    the metallization 3 of the contact bottom can be for example made of Ni, Ti, or their alloys (Ni 2 P, Ni 3 P, NiGe, TiP, TiGe,;
    - the diffusion barrier at F and / or the bonding layer at W 4 can be made of TiN, Ti / TiN, TaN, Ta / TaN, W;
    The filler metal 5 can be Cu or Al, AlCu, AlSi.
    This example of laser is illustrated in figure 9.
    Example of a vertically emitting VCSEL type laser component:
    It is recalled that in general, a laser diode with vertical cavity emitting by the surface, or VCSEL (vertical-cavity surface-emitting laser) is a type of semiconductor laser diode emitting a laser beam perpendicular to the surface, unlike conventional wafer emitting semiconductor lasers.
    This example of laser mainly comprises the same type of structure as that described in the previous example.
    However, in order to allow emission of laser radiation from above the structure, the upper contact is made in a circular manner.
    This example of a component comprises a silicon substrate 9 above which a base of second material III-V 2, which can be made of n-doped InP, is produced and a mesa 1 comprising a quantum multi-well structure which can be based on InGaAsP, AIGaAs, GaAs. , InGaAsN and a layer of p-doped InGaAs, the nature of the materials III-V fixes the emission wavelength.
    The dielectric 8 can be made of SiN, SiO 2 , of a planarizing type polymer, for example based on BCB.
    The metallization 3 of the contact bottom may for example be made of Ni, Ti, or their alloys (Ni 2 P, Ni 3 P, NiGe, TiP, TiGe, etc.).
    The diffusion barrier at F and / or the bonding layer at W 4 can be made of TiN, Ti / TiN, TaN, Ta / TaN, W.
    The filler metal 5 can be Cu or Al, AlCu, AlSi.
    The metallizations 3 and the elements 4 and 5 constitute the contacts C S up and Cînf.
    Thanks to the upper circular contact C sup , the laser beam can be extracted from the upper surface of the component.
    This example of laser is illustrated in figure 10.
    The integration of planar contacts typically opens the way for 3D components described above to 3D integration, by means of hybrid or direct bonding (for example photonics / electronics) or the transfer of chips by means of bumps.
    In the context of an lll-V / Si co-integration, the creation of a planarized back-end also makes it possible to envisage contact resumption on the devices of the lower levels (front side or intermetallic back-end for example) .
    An example is given in Figure 11 as part of a Photonic integration with the realization of all the contacts described above C sup and Ci n t, on the lll-V component (laser) and on the back-end of the silicon part. The additional contacts are ensured by the pads Pmî which connect metallic levels Mi, integrated in a dielectric
    8. Typically the substrate 91 can be silicon, the dielectric 90 can be SiO 2 .
    Example of a component used in solar cell type applications in which a series of different lll-V materials is stacked, making it possible to diversify the emission wavelengths
    This example of a component comprises a silicon substrate 9 above which are stacked as illustrated in FIG. 12:
    - A III-V 22 material located at a so-called lower level;
    - A III-V 21 material located at a so-called intermediate level;
    - A III-V 10 material located at a so-called higher level.
    Cint of material 22;
    Cint of material 21;
    C SU p of materials 10.
    The component includes:
    - contacts
    - contacts
    - contacts
    The Cint contacts are made by filling the stack of openings made successively: Oj S i, Oi S 2 and Oi S 3.
    The contacts Cint are produced by filling the stack of openings made successively: O ts i, O tS 2 The contacts C sup are produced by filling the opening:
    θSS
    Typically the materials III-V used can be in particular: InGaAsN, BlnGaAs, InGaN, GalnP, GalnAsP, GaAs.
    权利要求:
    Claims (22)
    [1" id="c-fr-0001]
    1. Method for producing a component comprising a structure of material (x) III-V on the surface of a substrate, said structure comprising at least one upper level of contact (N sup ) defined on the surface of a first material III-V (1) and a lower level of contact (Ninf) defined on the surface of a second material III-V (2), comprising:
    - successive operations of encapsulation by at least one dielectric of said structure;
    the production of at least one primary upper opening (O sp ) and at least one primary lower opening (Oi P ) in a dielectric so as to define contact bottom zones on said first material III-V and on said second material III-V;
    - The production of at least one secondary upper opening (Oss) and at least one secondary lower opening (Oj S ) in a dielectric so as to define zones of contact pads on said contact bottom zones;
    the at least partial filling with at least one metallic material of said at least primary upper opening, of said at least primary lower opening, of said at least secondary upper opening and of said at least secondary lower opening so as to produce:
    o at least one upper contact of said first material III-V in contact with the upper contact level and comprising at least one metallization of the upper contact bottom and at least one upper contact pad in contact with said metallization;
    o at least one lower contact of said second IIIV material in contact with said lower contact level and comprising at least one metallization of bottom contact base and at least one lower contact pad in contact with said metallization;
    - At least said upper contact and at least said lower contact are integrated in dielectric and have a surface defined in the same plane.
    [2" id="c-fr-0002]
    2. The production method as claimed in claim 1, in which the structure has a lower base made of second material III-V (2) and a mesa made of first material III-V (1) located above said base.
    [3" id="c-fr-0003]
    3. Production method according to one of claims 1 or 2, characterized in that it comprises the successive production of at least one primary upper opening and at least one primary lower opening.
    [4" id="c-fr-0004]
    4. Production method according to claim 3, characterized in that it comprises the simultaneous production of at least one secondary upper opening and at least one secondary lower opening.
    [5" id="c-fr-0005]
    5. Production method according to one of claims 1 or 2, characterized in that it comprises:
    - Encapsulation by a dielectric of an assembly comprising the material III-V (1) covered with a metallization (3) and the material III-V (2) covered with a metallization (3);
    - The production of at least one secondary lower opening (O is i) opposite the second material III-V (2);
    - The production of at least one secondary upper opening (Oss) above said first material III-V (1) and the production of at least one additional secondary lower opening (Ois2) above at least said secondary lower opening (Oj S i);
    - filling at least said secondary upper opening (O ss ), at least one additional secondary lower opening (Oi S 2) and at least said secondary lower opening (Oî s i) 3061354
    [6" id="c-fr-0006]
    6. Production method according to one of claims 1 to 5, characterized in that the structure comprising at least one lll-V said upper material (10), a lll-V said intermediate material (21), a second lll material -V said lower (22), the method comprises:
    - the production of at least one primary upper opening, at least one primary intermediate opening, at least one primary lower opening;
    - the production of at least one secondary upper opening, at least one secondary intermediate opening and at least one secondary lower opening;
    - filling of said openings.
    [7" id="c-fr-0007]
    7. The production method according to claim 6, in which:
    - At least said secondary lower opening comprises three portions of different dimensions (Oj S i, Oi S 2, 0.53);
    - At least said secondary intermediate opening comprises two portions of different dimensions (O ts i, O tS 2);
    - at least said secondary upper opening comprises a portion (O ss ) ·
    [8" id="c-fr-0008]
    8. Production method according to claim 3, characterized in that it comprises the following steps:
    - the encapsulation of said structure by a first dielectric;
    - The production of at least one primary lower opening (Ο, ρ ) leading to said second material III-V (2);
    - the metallization deposit on the surface of said first dielectric and on the surface of said second material III-V (2) defining a metallization of the bottom contact bottom and a first assembly (El);
    - the encapsulation of said first set (E1) by a second dielectric;
    - the planarization of said first encapsulated assembly;
    - The production of at least one secondary lower opening (O is i) leading to said metallization of the bottom contact bottom;
    - filling with at least one metallic material of said at least secondary lower opening defining at least one contact pad of said lower contact and a second assembly (E2):
    - the encapsulation of said second set (E2) by a third dielectric;
    - the production of at least one primary upper opening above said first material III-V (1);
    - the metallization deposit on the surface of said third dielectric material and of said upper opening defining a metallization of upper contact bottom and a third assembly (E3);
    - the encapsulation of said third assembly by a fourth dielectric;
    - the planarization of said third set;
    - The production of at least one secondary upper opening (Oss) above said metallization of the upper contact bottom and at least one upper opening (Oi S 2) above at least said contact pad of said lower contact;
    - filling with at least one metallic material of said at least secondary upper opening above said metallization of upper contact bottom and of said at least upper opening above at least said contact pad of said lower contact, defining at least one pad upper contact upper and at least one extension of lower contact pad, said upper contact (Cs Up ) and at least said lower contact (Cintj having a defined surface in the same plane.
    [9" id="c-fr-0009]
    9. Production method according to claim 3, characterized in that it comprises the following steps:
    - the encapsulation of said structure by a first dielectric;
    - The production of at least one primary upper opening (O sp ) leading to said first material III-V (1);
    - the metallization deposit on the surface of said first dielectric and on the surface of said first material III-V (1) defining an upper contact metallization and a first assembly (ET);
    - the encapsulation of said first assembly (ET) by a second dielectric;
    - the planarization of said first encapsulated assembly;
    - The production of at least one secondary upper opening (O ss ) leading to said metallization of the upper contact bottom;
    - filling with at least one metallic material of said at least secondary upper opening defining at least one contact pad of said upper contact and a second assembly (E2 ’);
    - making at least one primary lower opening (Ο, ρ ) above said second material III-V (2);
    - the metallization deposit on the surface of said first dielectric material and of said primary lower opening defining a lower contact metallization and a third assembly (E3 ’);
    - the encapsulation of said third assembly by a fourth dielectric;
    - the planarization of said third set;
    - making at least one secondary lower opening (Ois) above said bottom contact bottom layer;
    - filling of said at least secondary lower opening, defining at least one lower contact pad, said upper contact (Cs Up ) and at least said lower contact (Cinf) having a surface defined in the same plane
    [10" id="c-fr-0010]
    10. Production method according to one of claims 1 or 2, characterized in that it comprises:
    - the simultaneous production of at least one primary upper opening and at least one primary lower opening;
    - the simultaneous production of at least one secondary upper opening and at least one secondary lower opening.
    [11" id="c-fr-0011]
    11. Production method according to one of claims 1 to 10, characterized in that it comprises the production of an additional level of contact on the surface of said planar contacts, comprising:
    - an additional dielectric deposit (8);
    - the production of at least one lower additional opening and at least one upper additional opening;
    - filling of said additional openings with at least one metallic material to define at least one lower additional contact (Cint / supi) and at least one upper additional contact (C SU p / supi) ·
    [12" id="c-fr-0012]
    12. Production method according to one of claims 1 to 11, in which:
    - The primary lower openings have a width (D2) of between 20 μm and 50 μm;
    - The secondary lower openings have a width (D6) between 0.5 pm and 5 pm, preferably between 1 pm and 3 pm.
    [13" id="c-fr-0013]
    13. Production method according to one of claims 1 to 12, characterized in that the first material III-V and / or the second material III-V are chosen from: InP, In ^ xGaxAs (with 0 <x <1 ), GaAs, InAs, of GaSb, Ιη-ι-xGaxSb, ln x Gai-xAsi- y Py, Gai- x ln x P, ln x Gai- x Asi- y N y , B x ln y Gai- x . y As.
    [14" id="c-fr-0014]
    14. Production method according to one of claims 1 to 13, characterized in that the substrate is made of silicon.
    [15" id="c-fr-0015]
    15. Production method according to one of claims 1 to 14, in which the dielectric or dielectrics are chosen from: SiN, SiO 2 , AI 2 O 3 , a planarizing polymer which may be based on Benzocyclobutene (BCB) or SOG.
    [16" id="c-fr-0016]
    16. Production method according to one of claims 1 to 15, in which the deposition of a metal such as Ni 2 P, Ni 3 P, NiGe, TiP, TiGe is carried out in said primary openings.
    [17" id="c-fr-0017]
    17. Production method according to one of claims 1 to 15, in which the deposition of a metal such as Ni, Ti and an alloy such as NiPt, NiTi, NiCo is carried out in said primary openings.
    [18" id="c-fr-0018]
    18. Production method according to one of claims 1 to 16, in which the metallization deposit is followed by a heat treatment to form one or more intermetallic compound (s)
    [19" id="c-fr-0019]
    19. Production method according to one of claims 1 to 18, characterized in that the filling operations comprise:
    the deposition of a diffusion barrier which may be composed of one or more layers of material chosen from: TiN, Ti / TiN, TaN, Ta / TaN, W;
    - the deposition of a filler metal chosen from: W, Cu, Al, AlCu, AISi.
    [20" id="c-fr-0020]
    20. Production method according to one of claims 1 to 19, wherein the component being a laser, said method comprises an operation for producing a guide (91) of semiconductor material which may be Si, in a dielectric substrate (90) possibly in SiO 2 .
    [21" id="c-fr-0021]
    21. Production method according to one of claims 1 to 19, wherein the component being a laser, said process comprises the production of a circular upper contact to allow the vertical emission of laser radiation, at the center of said upper contact.
    [22" id="c-fr-0022]
    22. Component obtained according to the method of one of claims 1 to 21.
    1/14
    Non-planar contacts and noble metal compounds
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    同族专利:
    公开号 | 公开日
    JP2020502788A|2020-01-23|
    US20200274321A1|2020-08-27|
    CN110291616A|2019-09-27|
    FR3061354B1|2021-06-11|
    CA3047883A1|2018-06-28|
    WO2018115510A1|2018-06-28|
    EP3559981A1|2019-10-30|
    US11075501B2|2021-07-27|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US6596616B1|2002-04-19|2003-07-22|Motorola, Inc.|Method for forming serrated contact opening in the semiconductor device|EP3809543A1|2019-10-16|2021-04-21|TRUMPF Photonic Components GmbH|Method of fabricating a vcsel device and vcsel device|TWI267946B|2005-08-22|2006-12-01|Univ Nat Chiao Tung|Interconnection of group III-V semiconductor device and fabrication method for making the same|
    US9595805B2|2014-09-22|2017-03-14|International Business Machines Corporation|III-V photonic integrated circuits on silicon substrate|
    EP3460849A1|2014-11-24|2019-03-27|Artilux Inc.|Monolithic integration techniques for fabricating photodetectors with transistors on same substrate|FR3084774B1|2018-08-01|2021-08-27|Commissariat Energie Atomique|THERMALLY STABLE OHMIC CONTACT PROCESS ON INP OR INGAAS SEMICONDUCTOR|
    FR3109020B1|2020-04-06|2022-02-25|Scintil Photonics|PHOTONIC DEVICE FOR ESTABLISHING LIGHT RADIATION COMPRISING AN OPTICAL MODE IN A WAVEGUIDE|
    法律状态:
    2018-01-02| PLFP| Fee payment|Year of fee payment: 2 |
    2018-06-29| PLSC| Publication of the preliminary search report|Effective date: 20180629 |
    2019-12-31| PLFP| Fee payment|Year of fee payment: 4 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 5 |
    2021-12-31| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1663133A|FR3061354B1|2016-12-22|2016-12-22|COMPONENT REALIZATION PROCESS INCLUDING III-V MATERIALS AND COMPATIBLE SILICON INDUSTRY CONTACTS|
    FR1663133|2016-12-22|FR1663133A| FR3061354B1|2016-12-22|2016-12-22|COMPONENT REALIZATION PROCESS INCLUDING III-V MATERIALS AND COMPATIBLE SILICON INDUSTRY CONTACTS|
    EP17822326.9A| EP3559981A1|2016-12-22|2017-12-22|Process for producing a component comprising iii-v materials and contacts compatible with silicon process flows|
    CN201780085813.7A| CN110291616A|2016-12-22|2017-12-22|Preparation includes the method for the element of III-V material and the contact compatible with silicon technology process|
    JP2019528511A| JP2020502788A|2016-12-22|2017-12-22|Device including III-V material and process for forming contacts compatible with silicon process|
    PCT/EP2017/084529| WO2018115510A1|2016-12-22|2017-12-22|Process for producing a component comprising iii-v materials and contacts compatible with silicon process flows|
    CA3047883A| CA3047883A1|2016-12-22|2017-12-22|Process for producing a component comprising iii-v materials and contacts compatible with silicon process flows|
    US16/472,136| US11075501B2|2016-12-22|2017-12-22|Process for producing a component comprising III-V materials and contacts compatible with silicon process flows|
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